1. Field of the Invention
The present invention generally relates to memory devices. More specifically, the present invention relates to magnetoresistive random access memory (MRAM) devices.
2. Description of the Related Art
In a magneto-resistive random access memory (MRAM) device, a plurality of memory cells (i.e., MRAM cells) is typically arranged in a cross-point array, wherein each MRAM cell is sandwiched at an intersection of bit and word lines facilitating the read and write operations of the MRAM device. Such bit and word lines are known as “global bit lines” and “global word lines”, respectively.
An MRAM cell generally comprises a magnetic structure known as a “magnetic tunnel junction” (MTJ). In the MRAM cell, information is stored in the form of a direction of magnetization in a magnetic layer of the MTJ. Stored information may be preserved for long periods of time without use of sources of energy.
The MTJ comprises soft and hard magnetic layers that are separated by an insulating non-magnetic tunnel layer. Writing information in the MRAM cell is performed by magnetizing the soft magnetic layer in either one of two opposing directions, while the hard magnetic layer permanently maintains its state (i.e., direction) of magnetization. Stored information may be read by sensing the electrical resistance of the MTJ, which differs whether the magnetic layers are magnetized in the same or opposing directions. Magnetic fields used for operating the MRAM cell are created using programming currents propagating along the global bit and word lines (“write” operation) or a current that passes through the MTJ (“read” operation).
FIG. 1A depicts a schematic diagram of a portion of a typical cross-point MRAM array 100. The images in FIG. 1A are not depicted to scale and are simplified for illustrative purposes. The MRAM array 100 may be formed on a substrate 102 (shown using phantom lines), for example, a semiconductor substrate, such as a silicon (Si) substrate, and the like. The MRAM array 100 generally comprises a plurality of MRAM cells 104, a plurality of bit lines 108, and a plurality of word lines 112, as well as dielectric layers (not shown) providing electrical isolation and environmental protection for the MRAM cells and global lines 108, 112. The MRAM array 100 may comprise up to, for example, 2048 or more MRAM cells and, correspondingly, global bit and word lines. Herein the global bit lines 108 and global word lines 112 are identified using the same reference numerals, except that the suffixes “k−1”, “k”, “k+1”, and so on have been added to differentiate between adjacent lines.
An MRAM cell 104 generally comprises a magnetic tunnel junction (MTJ) 114 having a thin non-magnetic dielectric layer 118 sandwiched between a soft magnetic layer 116 and a hard magnetic layer 120. The layers 116 and 120 are known as a “free magnetic layer” and a “reference magnetic layer”, respectively. The MRAM cell 104 may also comprise optional film electrodes (not shown) to enhance electrical coupling between the MTJ 114 and global lines 108, 112. The magnetic orientation of the free magnetic layer 116 can be changed by superposition of the magnetic fields caused by programming currents 106 and 110 propagating along the respective bit line 108K and word line 112K of the cross-point MRAM array 100. However, the programming currents 106, 110 cannot change the magnetic orientation of the reference layer 120. Information is stored in the MTJ 114 by changing the orientation of magnetization of the free magnetic layer 116 relatively to the reference layer 120. When orientations of magnetization in the layers 116 and 120 are the same, the MTJ 114 has low electrical resistance. Such a resistance is high when the layers 116 and 120 are magnetized in opposite directions.
FIG. 1B depicts a schematic equivalent circuit 150 of the portion of the MRAM array 100 shown in FIG. 1A. The circuit 150 is conventionally simplified for illustrative purposes. The circuit 150 generally comprises conductors (global bit lines) 108K−1–108K+2 that form a cross-point array with the conductors (global word lines) 112K−1–112K+2 using a plurality of resistive elements 122. Each resistive element 122 represents the MRAM cell 104 that is disposed at intersection of the respective global bit and word lines of the MRAM array 100. The resistive element 122 has a resistance RMTJ=V/IMTJ, where V is a voltage applied across the MRAM cell, and IMTJ is a current through the MRAM cell.
During a write operation, non-selected MRAM cells form parasitic leakage current paths through the resistive elements 122, thereby causing program disturbs of the MRAM cells in the array 100 due to unprecise value of programming (i.e., write) currents.
During a read operation, the current IMTJ may have two discrete values IMTJ(0) and IMTJ(1), which correspond to the “0” and “1” memory states of the MRAM cell, respectively. Leakage currents flowing through the MRAM cells during the read operation have a value IL which is comparable with the value of the currents IMTJ(0) and IMTJ(1). The currents IL are undesirable leakage currents that reduce the signal-to-noise (S/N) ratio of the read operation and cause program disturbs in the array 100.
Intensity of the cross-talk between the MRAM cells increases with a number of the cells in the MRAM array. Such cross-talk reduce a signal-to-noise (S/N) ratio of read and write operations and limit the information capacity of the MRAM device. In the MRAM array 100 having N×N=N2 MRAM cells, during the write operation, a total leakage current IΣ from a global bit line is approximately N times greater than the single cell current IL, i.e., IΣ≅NIL. To be functional, the MRAM array 100 comprises MRAM cells having a high resistance RMTJ. However, during the read operation, the current flowing through such MRAM cells (i.e., read current) is small and difficult to sense.
As such, high leakage currents IL and high resistance RMTJ result in a low S/N ratio of read and write operations in the MRAM device that uses the array 100. Generally, the S/N ratio in conventional cross-point MRAM arrays (e.g., array 100) becomes worse in high-density arrays where bit lines are coupled to a greater number of the MRAM cells.
Therefore, there is a need in the art for a magneto-resistive random access memory (MRAM) array having low leakage currents.